This invention relates to semiconductor integrated circuit structures. More particularly, it is concerned with electrical interconnections between elements of semiconductor integrated circuits.
As improvements have been made in the techniques of fabricating semiconductor integrated circuits it has been possible to produce elements with closer tolerances permitting elements to be of smaller size, thus making more efficient use of the semiconductor wafer. The width of metallic interconnections between elements can also be reduced. The resulting smaller cross-sectional areas of the metallic interconnections decreases their electrical conductance and tends to reduce overall circuit performance. Compensating by increasing the thickness of the deposited metallic interconnections introduces various difficulties. Mechanical strain in the metallic structure may cause peeling of the metal from the surface of the wafer. Thick layers of metal are difficult to etch with sufficient precision so as to maintain the lateral relationships. Steep vertical steps in the metallic interconnections are difficult to cover in a reliable manner with insulating layers. Furthermore, the uneven steps of the non-planar surface present difficulties in obtained proper alignment and definition when employing photolithographic processes.